ACA Advanced Computer Architectures
Course information
Complete course name: 088949 - ADVANCED COMPUTER ARCHITECTURES (SILVANO CRISTINA) Profesor: Cr...
MIPS architecture and pipeline
The MIPS processor is a RISC (Reduced Instruction Set Computer) which follows a LOAD/STORE archit...
Pipeline hazards
An hazard is created when there is a dependence between instructions and the instructions are clo...
Exception handling
The following type of exceptions, interrupts and faults are considered: I/O device request; Invo...
Static Branch Prediction
Static branch prediction is done and fixed at compile time. This technique is typically used when...
Dynamic Branch Prediction
The basic idea of dynamic branch prediction is to use the past branch behavior to predict the fut...
Caches
The main goal of caches is to increase the performance of a computer through the memory system in...
Improving cache performance
$$\text{AMAT} = \text{Hit Time} + \text{Miss Rate} \times \text{Miss Penalty}$$ In order to impro...
Dependences
Dependences In an assembly code there may be varius dependences between instructions. The depende...
Instruction level parallelism
Multi-cycle pipelining We make the following basic assumptions: single-issue processors: one in...
Scoreboard
In the scoreboard architecture we divide the ID stage: Issue: decode instructions, check for st...
Tomasulo Algorithm
Tomasulo introduces the Implicit Register Renaming to avoid WAR & WAW hazards. In the Tomasulo ar...
Other register renaming techniques
Tomasulo implements an implicit register renaming: the code is not changed and there is dynamic l...
Speculation and reorder buffer
Hardware-based Speculation Extends the ideas of dynamic scheduling beyond branches combining 3 co...