Multi-cycle pipelining

We make the following basic assumptions:

single-issue processors: one instruction fetch per cycle
in order issue of instructions
Execution stage may require multiple cycles depending on the operation (i.e. multiply operations are longer than add/sub)
Memory stage might require multiple cycles access time due to cache misses

If the processor is also in order commit of instructions then the precise exception model is preserved and WAR/WAW are avoided.

But the commit can be made out of order: we need to check the generation of WAR/WAW hazards.