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Multi-cycle pipelining and multiple issue pipeline

Multi-cycle pipelining

We make the following basic assumptions:

  • single-issue processors: one instruction fetch per cycle
  • in order issue of instructions
  • Execution stage may require multiple cycles depending on the operation (i.e. multiply operations are longer than add/sub)
  • Memory stage might require multiple cycles access time due to cache misses

Commit type

If the processor is also in order commit of instructions then the precise exception model is preserved and WAR/WAW are avoided.

But the commit can be made out of order: we need to check the generation of WAR/WAW hazards.

Multiple issue pipeline

To reach higher performance more parallelism must be used. Dependences must be solved and instructions must be re-ordered so as to achive the highest parallelism of instructions execution compatible with available resources.

In an ideal multiple-issue pipeline the ideal CPI is less than one: $CPI < 1$.

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