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MIPS architecture and pipeline

The MIPS processor is a RISC (Reduced Instruction Set Computer) which follows a LOAD/STORE architecture where the ALU operands come from the CPU general purposes registers and they cannot come directly from the memory: load data from the memory to the registers and store data from the registers to the memory.

MIPS pipeline

The MIPS architecture has a 5 stages pipeline:

  1. Instruction Fetch (IF): Send the content of the program counter (PC) register to the instruction memory and fetch the current instruction. Then update the PC adding 4 (each instruction is 4 bytes long)
  2. Instruction Decode (ID): Decode the current instruction and read from the register file the value of the registers
  3. Execution (EX): The ALU operates on the operands prepared in the previous steps.
  4. Memory access (MEM): Load and store instructions require to access the memory.
  5. Write back (WB): Write to the register file.
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