ACA Advanced Computer Architectures

Complete course name : 088949 - ADVANCED COMPUTER ARCHITECTURES (SILVANO CRISTINA) Profesor : Cristina Silvano Tutor : Gerardo Pelosi Accademic year : 2021-2022 Recordings : link to webeep Webeep :…

The MIPS processor is a RISC (Reduced Instruction Set Computer) which follows a LOAD/STORE architecture where the ALU operands come from the CPU general purposes registers and they cannot come…

An hazard is created when there is a dependence between instructions and the instructions are close enouth that the overlap caused by pipelining would change the order of access to the operands…

The following type of exceptions, interrupts and faults are considered: I/O device request; Invoking OS system call from a user program; Tracing instruction execution; Integer arithmetic…

Static branch prediction is done and fixed at compile time . This technique is typically used when the branch behavior for the target application is highlyh predictable at compile time. Note: we…

The basic idea of dynamic branch prediction is to use the past branch behavior to predict the future. We need hardaware to dynamiccaly predict the outcome of a branch: the prediction will depend on…

The main goal of caches is to increase the performance of a computer through the memory system in order to: Provide the user the illusion to use a memory that is simultaneously large and fast Provide…

$$\text{AMAT} = \text{Hit Time} + \text{Miss Rate} \times \text{Miss Penalty}$$ In order to improve the AMAT we need to: Reduce the miss rate Reduce the miss penalty Reduce the hit time The overall…

Dependences In an assembly code there may be varius dependences between instructions. The dependences are a property of the code , while hazards may arise from these dependeces depending on the…

Multi-cycle pipelining We make the following basic assumptions: single-issue processors: one instruction fetch per cycle in order issue of instructions Execution stage may require multiple cycles…

In the scoreboard architecture we divide the ID stage : Issue : decode instructions, check for structural hazards Read operands (RR) : wait until there are no data hazards, then read operands Another…

Tomasulo introduces the Implicit Register Renaming to avoid WAR & WAW hazards . In the Tomasulo architecture some buffers called Reservation Stations (RS) are placed in front of the functional…

Tomasulo implements an implicit register renaming : the code is not changed and there is dynamic loop unrolling . But there are other possible techniques for register renaming Compiler…

Hardware-based Speculation Extends the ideas of dynamic scheduling beyond branches combining 3 concepts: Dynamic branch prediction Speculation to enable the execution of instructions before the…